This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light and not as admissions of prior art.
Integrated circuits can be found in virtually any electronic device. For example, integrated circuits such as microprocessors and digital memory chips are present in products such as computers, cell phones, and microwave ovens. Since their first introduction over a half century century ago, integrated circuits have progressively become smaller and increasingly more densely populated. The increase in density provides numerous advantages, including the ability for smaller chips to perform the same functionality as larger chips. Additionally, the smaller size increases performance and reduces power consumption. Specifically, with smaller size, the electrical paths are shorter, allowing low power logic to be used at fast switching speeds.
Achieving progressively smaller structure size on the chips, and thus producing smaller chips, has become increasingly difficult and costly due, at least in part, to reaching physical limitations of standard fabrication techniques. New and improved processes are constantly being proposed to further reduce cost as well as size.
Typically, the integrated circuit manufacturing process includes at least three main processes: 1) patterning; 2) adding materials; and 3) removing materials. The patterning process is primarily achieved by employing photolithography. Through the patterning process, various regions are defined that eventually serve as the components, such as transistors and traces, of the integrated circuit. The process of adding materials includes depositing or growing material on a substrate to create multiple layers. One layer typically included in an integrated circuit is a dielectric layer, which may be formed as an oxide. The process of removing material generally includes an etching process. It is through the etching process that material in regions defined by the pattern is removed to form various structures.
Etching may be performed in one of two methods: wet etching or dry etching. In dry etching, a plasma etchant is used to remove material in an anisotropic manner, meaning that the etching occurs in a single direction downward though the material. Even though the dry etching process is more costly than wet etching, it is more often employed due to the anisotropic etching characteristic. The anisotropic nature of dry etching allows for better resolution compared to that achievable through wet etching and consequently provides the ability to create smaller, well-defined structures. As discussed above, the smaller the geometries, the more efficient the integrated circuit may be.
Current techniques capable of achieving small-scale geometries include the 193 nm dry etch and the 193 nm emersion techniques. The 193 nm dry etch is capable of achieving geometries with a lower limit resolution of about 65 nm, while the 193 nm emersion technique is capable of achieving geometries with a lower limit resolution of about 45 nm. Yet another technique, the EUV technique, claims the capability of achieving even smaller geometries, although its lower limit remains unproven.
Disadvantageously, the above-mentioned techniques are relatively costly and are constrained by limits in resolution capability. The number of iterative steps required in integrated circuit manufacturing typically correlates directly with the cost of production. To create a single structure, for example, multiple photomasks may be necessary using conventional techniques. Specifically, to create a via or a hole, for example, a first photomask may be used to create a trench, and a second mask is employed to etch through the layer, within the trench to create the via. Each use of a new photomask requires the removal of the wafer from the etch chamber for the application of the new photomask, thus, increasing cost. Further, employing multiple masks increases the risk of misalignment which may result in fabrication defects.